Title :
A HyperTransport chip-to-chip interconnect tunnel developed using SystemC
Author :
Castonguay, Ami ; Savaria, Yvon
Author_Institution :
Ecole Polytech. de Montreal, Que., Canada
Abstract :
This paper presents a HyperTransport (HT) tunnel developed in hardware with SystemC. HT is an excellent technology for implementing flexible high performance system switch fabrics applicable to rapid system prototyping. An overview of the proposed architecture is presented, followed by synthesis results. Performance analysis shows that, when configured as an 8-bit link and implemented in a 0.18μm CMOS standard cell technology, the design can operate at 400 mega transfers/s. This paper discusses the advantages and drawbacks of working with SystemC to perform large scale hardware implementations.
Keywords :
CMOS integrated circuits; hardware description languages; integrated circuit interconnections; performance evaluation; CMOS standard cell technology; HyperTransport tunnel; SystemC; chip-to-chip interconnect; high performance system; large scale hardware implementation; rapid system prototyping; CMOS technology; Clocks; Cyclic redundancy check; Delay; Fabrics; Hardware; Network topology; Performance analysis; Prototypes; Switches;
Conference_Titel :
Rapid System Prototyping, 2005. (RSP 2005). The 16th IEEE International Workshop on
Print_ISBN :
0-7695-2361-7
