• DocumentCode
    2029302
  • Title

    On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition

  • Author

    Glette, Kyrre ; Torresen, Jim ; Yasunaga, Moritoshi ; Yamaguchi, Yoshiki

  • Author_Institution
    Dept. of Informatics, Oslo Univ.
  • fYear
    2006
  • fDate
    15-18 June 2006
  • Firstpage
    373
  • Lastpage
    380
  • Abstract
    To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an on-chip processor. This gives higher flexibility compared to implementing an evolutionary algorithm directly in hardware, since the parameters and behaviour of the algorithm can easily be changed, and complex operators are more feasible to implement. In this paper a Xilinx MicroBlaze soft core processor is used, and the system is implemented in a Xilinx FPGA. A suitable hardware architecture for image recognition has been proposed, and it is applied to a face recognition task. Data buses and higher level functions have been utilized in order to reduce the search space for the evolutionary algorithm. Experiments have been performed on the physical device, with software running in parallel with fitness computation in digital logic. Results show that the MicroBlaze system evolves at half the speed of a Pentium M system running at 17 times the FPGA clock frequency. The distinction of a certain face from others is performed at 94.9% accuracy. In addition, the possibilities for evolutionary adaptation over time are explored by introducing changes in the training set. The system shows ability to adapt to these changes
  • Keywords
    computer architecture; digital signal processing chips; evolutionary computation; face recognition; field programmable gate arrays; system buses; system-on-chip; Xilinx FPGA; Xilinx MicroBlaze soft core processor; data buses; digital logic; evolutionary algorithm; face recognition; hardware architecture; image recognition; on-chip processor evolution; single-chip evolvable hardware system; soft processor core; Computer architecture; Concurrent computing; Data buses; Evolutionary computation; Face recognition; Field programmable gate arrays; Hardware; Image recognition; Software performance; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Adaptive Hardware and Systems, 2006. AHS 2006. First NASA/ESA Conference on
  • Conference_Location
    Istanbul
  • Print_ISBN
    0-7695-2614-4
  • Type

    conf

  • DOI
    10.1109/AHS.2006.55
  • Filename
    1638187