Title :
An IDDQ-fault location scheme
Author :
Chang, Tsin-Yuan ; Chen, Weihong
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
In this work, an IDDQ fault location scheme is proposed and implemented in a chip to locate a single faulty branch (either a VDD branch or a GND branch or both) with a three-pattern test by using a hardware approach, which can be applied to the redundant VLSI structure for yield enhancement in the repairable design. The fault model includes IDDQ fault with or without single stuck on/off fault in the added transistors. The yield analysis of the proposed scheme is also presented
Keywords :
CMOS digital integrated circuits; VLSI; fault diagnosis; fault location; integrated circuit testing; integrated circuit yield; logic testing; redundancy; CMOS VLSI chip; GND branch; IDDQ-fault location scheme; VDD branch; fault model; redundant VLSI structure; repairable design; single faulty branch; single stuck on/off fault; three-pattern test; yield analysis; yield enhancement; CMOS logic circuits; Circuit faults; Fault detection; Fault location; Fault tolerance; Hardware; MOS devices; Semiconductor device modeling; Testing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.594137
