• DocumentCode
    2030054
  • Title

    Embedded tutorial 3: Statistical learning for analog circuit testing

  • Author

    Stratigopoulos, Haralampos-G

  • Author_Institution
    TIMA Lab., CNRS, Grenoble, France
  • fYear
    2011
  • fDate
    6-8 April 2011
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    Summary form only given. The test cost per transistor in integrated circuits (IC) has remained practically steady during the past decades, unlike the manufacturing cost per transistor which is gradually being reduced. In recent years, there have been anecdotal cases where the test cost actually surpasses the overall manufacturing cost. To this end, test cost reduction is a significant driving force for the deployment of ICs in a wider range of applications for the broad public. It is also a fact that the cost for testing the analog portions of an IC can amount up to 50% of the total test cost, despite that analog circuits occupy typically less than 5% of the die area. This shows that analog test is in the coming years an area for industry focus, innovation and improvement.
  • Keywords
    analogue integrated circuits; integrated circuit testing; statistical testing; IC deployment; analog circuit testing; integrated circuits; manufacturing cost; statistical learning; Analog circuits; Integrated circuits; Loss measurement; Manufacturing; Testing; Transistors; Tutorials;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on
  • Conference_Location
    Athens
  • Print_ISBN
    978-1-61284-899-0
  • Type

    conf

  • DOI
    10.1109/DTIS.2011.5941406
  • Filename
    5941406