A novel parallel architecture for low voltage-low power DLL-based frequency multiplier

Author

Gholami, Mohammad ; Sharifkhani, Mohammad ; Hashemi, Mohsen

fYear

2011

fDate

6-8 April 2011

Firstpage

1

Lastpage

4

Abstract

New architecture for a DLL based frequency multiplier for wireless transceivers presents in this paper. This architecture has the advantages of occupy low area, low power, low voltage and low phase noise. DLLs are first ordered systems, so good stability can obtain in this design. This structure also can be used for generating big multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. As an example, the multiplier is adopted to create the 13 times of the reference frequency. The circuit level design is presented. Also power consumption trade-offs are reported. Simulation results confirm the analytical predictions. The proposed DLL-based frequency multiplier is implemented in a 0.13 um CMOS Technology.

Keywords

CMOS integrated circuits; delay lock loops; frequency multipliers; low-power electronics; parallel architectures; phase noise; radio transceivers; CMOS technology; circuit level design; frequency multiplier; low phase noise; low voltage-low power DLL; parallel architecture; power consumption; reference frequency; size 0.13 mum; wireless transceivers; Delay; Frequency synthesizers; Jitter; Logic gates; Phase frequency detector; Phase noise; Time frequency analysis; DLL; Delay locked loop; Frequency Multiplier; Jitter; Phase noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on

Conference_Location

Athens

Print_ISBN

978-1-61284-899-0

Type

conf

DOI

10.1109/DTIS.2011.5941408

Filename

5941408