DocumentCode
2030351
Title
Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator
Author
Guilley, Sylvain ; Meynard, Olivier ; Nassar, Maxime ; Duc, Guillaume ; Hoogvorst, Philippe ; Maghrebi, Houssem ; Elaabid, Aziz ; Bhasin, Shivam ; Souissi, Youssef ; Debande, Nicolas ; Sauvage, Laurent ; Danger, Jean-Luc
Author_Institution
Dept. COMELEC, TELECOM ParisTech, Paris, France
fYear
2011
fDate
6-8 April 2011
Firstpage
1
Lastpage
6
Abstract
Implementation-level attacks are nowadays well known and most designers of security embedded systems are aware of them. However, both the number of vulnerabilities and of protections have seriously grown since the first public reporting of these threats in 1996. It is thus difficult to assess the correct countermeasures association to cover all the possible attack paths. The goal of this paper is to give a clear picture of the possible adequation between actually risks and mitigation techniques. A specific focus is made on two protection techniques addressing primarily side-channel attacks: masking and hiding. For the first time, we provide with a way to estimate a tradeoff depending on the environmental conditions (amount of noise) and on the designer skills (ability to balance the design). This tradeoff is illustrated in a decision diagram, helpful for the security designer to justify choices and to account for the cost overhead.
Keywords
cryptography; embedded systems; attack path; cost overhead; decision diagram; designer skill; environmental condition; hiding attack; implementation-level attack; masking attack; mitigation technique; noise; protection technique; risk; security embedded system; side-channel attack; vade mecum; Analytical models; Correlation; Cryptography; Mathematical model; Noise; Software; Timing; Implementation-level attacks; comparison of countermeasures; decision diagram for the designer; hiding and masking; leakage metric; side-channel attacks;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on
Conference_Location
Athens
Print_ISBN
978-1-61284-899-0
Type
conf
DOI
10.1109/DTIS.2011.5941419
Filename
5941419
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