How significant will be the test cost share for 3D die-to-wafer stacked-ICs?

Several challenges must be overcome before high volume production of the 3D Stacked-ICs (3D-SIC) can be realized. A key challenge is to guarantee the required product quality at minimal overall cost. Testing, which is an integral part of 3D-IC manufacturing, should be performed in such way that its cost contribution is optimal. This paper investigates the impact of different test moments for pre-bond and post-bond stacks (resulting into different test flows) on the overall cost of die-to-wafer (D2W) 3D-SICs. The investigation is carried out for a wide range of die yields and stack sizes. Moreover, a breakdown of the cost into manufacturing, test and packaging costs offers a more detailed picture of the 3D overall cost. Our simulation results show that overall cost in D2W stacking strongly depends on the selected test flow; test flows with pre-bond and post-bond tests show a higher test cost share, but a significant reduction in the overall 3D-SIC cost. In addition, the cost breakdown for our reference process reveals that the manufacturing cost is most dominant (between 76% and 85%), followed by test (between 13% and 19%). Moreover, the results show that the share of test and packaging decreases as the manufacturing becomes mature and the yield increases, and that both manufacturing and test cost share increases, while the packaging cost share decreases for higher stack sizes.