Accelerated compact test set generation for three-state circuits

Most published ATPG methods cannot handle three-state primitives, generate too large test sets, or require excessive CPU time. An efficient ATPG system was introduced by M.H. Konijnenburg et al. (1995) and J.Th. van der Linden et al. (1994), which can handle non-Boolean primitives, generates compact test sets, within affordable CPU time. In this paper, the system is extended to handle pulled and wired buses, in addition to pure three-state buses. These bus types are widely used in industrial circuits. Furthermore five techniques for test generation are proposed to accelerate (compact) ATPG. Experimental results demonstrate that these new techniques are useful: ATPG times for compact test set generation are decreased up to 50% compared to that reported previously by Konijnenburg et al. and fault efficiencies above 99% can be obtained for even the largest circuits