A standard-cell library suite for deep-deep sub-micron CMOS technologies

The continuous scaling of CMOS transistor and interconnect geometries brings to light novel challenges regarding the design of VLSI systems in the nanoscale era. On the other hand, most of the forthcoming deep-deep submicron technologies are not yet mature to be used for fabrication. Hence, the development of standard-cell libraries at the nanometer regime is emerging, in order to estimate the behavior of complex systems in short-term technology nodes. In this paper, we introduce a standard-cell library generator flow for sub-65nm nodes, based on scaling rules presented in the literature. Our goal is to create a set of complete standard cell libraries enabling the design of large digital systems in technologies not yet available for fabrication. The generated libraries are compatible with the state-of-the-art industrial tool flows and they have been evaluated by benchmarks of medium and large complexity.