Techniques to Enhance Cache Performance Across Parallel Program Sections

Private caches are critical components in high per formance multiprocessor systems. However, it has been found that, when executing a parallel program, individual processors are very difficult to attain high cache hit ratio from one program section to another; therefore sophisti cated software coherence schemes are not cost effective. In this study, trace-driven simulation has been used to evaluate various less sophisticated compiler and software techniques which can enhance this inter-section locality in parallel executions. We found that the locality can be substantially im proved through the following ways of altering the sched uling of iterations in parallel DO loops among the executing processors: i) assignment of iterations in chunks, ii) reversed execution of parallel loops, and Hi) interchange inner and outer loops. These can be done manually by a programmer or automatically by a parallelizing compiler. Moreover, we also propose a software coherence scheme which can attain the maxi mum inter-section locality for read-only shared data.