Reconfigurable Branch Processing Strategy in Super-scalar Microprocessors

In this paper, we develop a model for measuring branch performance on super-scalar processors. This model takes the form of CP I equations for different branch processing strategies. This model is the basis for a proposed design wherein the branch processing strategy in a processor can be reconfigured for optimal performance over a varying application load. There are nine parameters which are required to describe performance of a given branch processing method -four are dependent primarily on the processor architecture, two depend on the application program, and three depend primarily on the branch instance. The highest performance branch prediction algorithm can be determined by a combination of application profiling and runtime statistic gathering