BIST fault diagnosis in scan-based VLSI environments

Existing BIST diagnostic techniques assume the existence of a very few bit errors in a test response sequence. This assumption is unrealistic since in a practical BIST environment a single defect in a circuit can usually cause hundreds or thousands of errors in a test response sequence. This paper presents a novel BIST fault diagnostic technique for scan-based VLSI devices, without making the above assumption. Based on faulty signature information our scheme guarantees correct identification of the scan flops that capture errors during test, regardless of the number of errors the circuit may produce. In addition, it is also capable of identifying the failing test vectors with a better diagnostic capacity than existing techniques. The proposed scheme does not assume any specific fault model. Thus, it is able to diagnose all voltage-detectable faults. This paper analyzes the efficiency of the scheme in terms of diagnostic coverage. Experimental results on several large ISCAS89 benchmark circuits and industrial circuits are also included