DocumentCode
2032140
Title
Performance Evaluation of Memory Caches in Multiprocessors
Author
Chen, Yung-Chin ; Veidenbaum, Alexander V.
Author_Institution
MIPS Technologies, Inc., Silicon Graphics, Inc., Mountain View, CA
Volume
1
fYear
1993
fDate
16-20 Aug. 1993
Firstpage
184
Lastpage
187
Abstract
Large-scale MIN-based shared-memory multiprocessor systems have long shared memory latency. Private caches can improve memory access latency but they may suf fer from the cache coherence problem and potentially lower data locality due to data sharing and multiproces sor scheduling. These two problems also increase shared memory load and may result in frequent memory stalls. In this paper, we evaluate the performance of memory caches, a cache memory placed in front of shared memory, in a large-scale multiprocessor system in the presence of pro cessor caches. The memory cache is shown to have good performance and scalability.
Keywords
Cache memory; Delay; Graphics; Large-scale systems; Multiprocessing systems; NASA; Parallel processing; Random access memory; Scalability; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing, 1993. ICPP 1993. International Conference on
Conference_Location
Syracuse, NY, USA
ISSN
0190-3918
Print_ISBN
0-8493-8983-6
Type
conf
DOI
10.1109/ICPP.1993.142
Filename
4134136
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