Efficient baseband implementation on an SDR platform

We address the issues related to implementation of baseband signal processing algorithms on an SDR platform with multiple parallel processors, such as the Intel´s X-GOLD™ SDR20 baseband processor. The basic idea is to reformulate the baseband signal processing algorithms such that they can be efficiently implemented on a parallel architecture. A hierarchical LTE initial synchronization scheme is taken as an example which involves algorithmic modules such as summation, maximum search, vector addition, cross-correlation, auto-correlation, FFT, FIR filter, etc. As can be shown, the computational complexity of an algorithm itself is vital and determines its implementability on a parallel SDR platform. Except for modules like summation, maximum search, vector addition, cross-correlation which can be parallelized straightforwardly, we show how to parallelize sequential and iterative algorithmic modules like autocorrelation and FFT. Challenges and future work are also discussed.