Title :
Conservative modeling of the contribution of spurious transitions to power dissipation in digital CMOS VLSI circuits
Author :
Tretz, Christophe ; Zukowski, Charles
Author_Institution :
Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Abstract :
To achieve optimum performance a number of CMOS design choices, such as the choice of logic family, requires a general model of the fraction of logic transitions that arise from spurious transitions (glitches). This fraction can then be used to estimate the additional power dissipation due to spurious transitions. Analysis and simulation of a ripple-carry adder is used to derive a conservative model for static circuits. Across most applications, a good conservative estimate for the fraction is 30 to 40% of the total number of logic transitions
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; VLSI; adders; integrated circuit modelling; digital CMOS VLSI circuits; logic transitions; modeling; power dissipation; ripple-carry adder; spurious transitions; Adders; CMOS digital integrated circuits; CMOS logic circuits; Clocks; Delay estimation; Logic design; Power dissipation; Power system modeling; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.594152
