A continuous-time switched-current ΣΔ modulator with reduced loop delay

Author

Luh, L. ; Choma, John

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA

fYear

1998

fDate

19-21 Feb 1998

Firstpage

286

Lastpage

291

Abstract

A novel architecture for a second-order continuous-time switched-current ΣΔ modulator is presented. The loop delay is reduced by predicting the states of the second integrator and feeding the predicted states to the comparator. The predicted states are generated by summing three scaled current mode signals. A gain-manager is used to accurately control the integrator gain to generate the predicted states and stabilize the system. A newly designed high-speed current-mode comparator is capable of summing the three scaled current inputs and comparing them. With a 50 MHz sampling rate, it has achieved 60 dB dynamic range (10-bit) at 1 MHz. The modulator has been fabricated in a 2 μm CMOS process with an active area of 0.37 mm². The power dissipation is 16.6 mW from a 5 V single power supply

Keywords

comparators (circuits); delays; integrating circuits; sigma-delta modulation; switched current circuits; 16.6 mW; 2 micron; 5 V; 50 MHz; active area; continuous-time switched-current ΣΔ modulator; dynamic range; high-speed current-mode comparator; integrator gain; loop delay; power dissipation; predicted states; scaled current mode signals; summing; CMOS process; CMOS technology; Circuits; Clocks; Control systems; Delay; Delta modulation; Dynamic range; Power dissipation; Power supplies; Signal generators; Signal sampling; Stability; Switches; Switching converters;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Conference_Location

Lafayette, LA

ISSN

1066-1395

Print_ISBN

0-8186-8409-7

Type

conf

DOI

10.1109/GLSV.1998.665270

Filename

665270