A Method of Manufacturing a Low Defect, Low Stress Pre-metal Dielectric Stack for High Reliability and MEMs Applications

Author

Naughton, John J. ; Nelson, Mark M.

Author_Institution

Technol. R&D, AMI Semicond., Inc., Pocatello, ID

fYear

2006

fDate

22-24 May 2006

Firstpage

88

Lastpage

92

Abstract

It is widely known in the semiconductor industry that CMP induced micro-scratches can cause not only an initial failure but also a long-term reliability problem. Silicon oxide films doped with boron and phosphorus have been standard in pre-metal dielectric stacks but are prone to CMP micro scratching. A novel film stack was developed utilizing a thick undoped PECVD cap layer to mitigate device failure and reliability problems. The sequence of depositing the integral film layers in conjunction with the densification proved critical in maintaining device performance

Keywords

boron; chemical mechanical polishing; dielectric materials; micromechanical devices; phosphorus; plasma CVD; reliability; silicon compounds; CMP microscratching; MEMS applications; PMD; boron; high reliability; integral film layers; manufacturing process; phosphorus; pre-metal dielectric stack; semiconductor doping; semiconductor industry; silicon oxide; thick undoped PECVD; Boron; Dielectrics; Electronics industry; Maintenance; Manufacturing; Semiconductor device manufacture; Semiconductor device reliability; Semiconductor films; Silicon; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

1-4244-0254-9

Type

conf

DOI

10.1109/ASMC.2006.1638729

Filename

1638729