DocumentCode :
2032478
Title :
Using ILA testing for BIST in FPGAs
Author :
Stroud, Charles ; Lee, Eric ; Konala, Srinivasa ; Abramovici, Miron
Author_Institution :
Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
fYear :
1996
fDate :
20-25 Oct 1996
Firstpage :
68
Lastpage :
75
Abstract :
We present an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays. The new architecture is easily scalable with increasing size of FPGAs and ensures routability of the various configurations required to completely test the FPGA in three test sessions. In addition, the BIST approach addresses RAM mode testing as well as testing the adder/subtractor modes in FPGAs
Keywords :
built-in self test; field programmable gate arrays; integrated memory circuits; iterated switching networks; logic testing; random-access storage; BIST; C-testable iterative logic arrays; FPGA; Field Programmable Gate Array; ILA testing; RAM mode testing; adder/subtractor modes; iterative logic array; programmable logic blocks; routability; test sessions; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Field programmable gate arrays; Logic testing; Read-write memory; System testing; Table lookup; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-3541-4
Type :
conf
DOI :
10.1109/TEST.1996.556946
Filename :
556946
Link To Document :
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