Title :
An analytical thermal and stress analysis tool for die attach optimization in GaN power amplifier (PA) applications
Author :
Quan Qi ; Monthei, D.
Author_Institution :
TriQuint Semicond., Inc., Hillsboro, OR, USA
Abstract :
Die attach is a crucial ingredient of the overall solution to ensure that a PA device can function with acceptable junction temperature during peak power operation over the target service life, while mitigating thermo-mechanical stresses incurred by the mismatch of coefficients of thermal expansion between GaN device and substrate materials during temperature excursion. Traditionally, thermal and stress analyses must be performed separately and with different numerical analysis tools. This process can be lengthy and time consuming and more often than not an optimized thermal solution will not coincide with an optimized mechanical solution. Such a dilemma provides the impetus for what is reported here: development of an analytical tool for concurrent thermal and stress analyses and quick turn die attach optimization. Thermal solutions are based on the approach reported by Muzychka et al. that accounts for general device level thermal spreading resistance; the infinite series summation solution was adapted to GaN device configurations that allows device design and die attach optimizations at the same time by, unlike numerical solutions, showing the individual contributing factors to the overall thermal resistances. If the input power level and user environment are known for a particular device, junction temperature may be calculated and used to calibrate the model accuracy with, say, high resolution IR thermal imaging measurement or independent FEA analysis. Once calibration is confirmed, trend prediction can then be performed to assess the impacts of different design parameters as well as die attach materials on the device thermal performance. Thermo-mechanical stress solutions are based on the bimetallic beam theories originally attributed to Timoshenko and later improved by Suhir and others. This 2D approach utilizes close-form analytical solutions and captures the dominant behavior of the stress distributions inside the die attach layer. For a given die attach ma- erial and bond-line-thickness (BLT), von Mises stress can be readily calculated and results for die attach materials can then be assessed side by side with the thermal analysis results. An iterative loop may be initiated based on the independent but yet integrated analysis methodologies presented here: thermal analysis to optimize the device design with selection of die attaches material and stress analysis to verify the selected die attach does not induce excessive stress under thermal loading. Iteration stops when the selected die attach achieves a balance among factors such as acceptable junction to case thermal resistance and lower die attach von Mises stress, in addition to cost, shelf life, processing condition, etc. considerations. A case study will be demonstrated to show how the developed tool can be applied to help shorten the die attach selection cycle with optimization and trend predictions.
Keywords :
III-V semiconductors; gallium compounds; infrared imaging; iterative methods; microassembling; power amplifiers; stress analysis; thermal analysis; thermal expansion; thermal resistance; wide band gap semiconductors; 2D approach; BLT; GaN; PA device; acceptable junction temperature; analytical thermal analysis tool; bimetallic beam theories; bond-line- thickness; close-form analytical solutions; device design; device thermal performance; die attach material; die attach optimization; general device level thermal spreading resistance; high resolution IR thermal imaging measurement; independent FEA analysis; infinite series summation solution; iterative loop; numerical analysis tools; peak power operation; power amplifier applications; stress analysis tool; substrate materials; target service life; temperature excursion; thermal expansion; thermal resistances; thermomechanical stresses mitigation; von Mises stress; Conferences; Decision support systems; Electronics packaging;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-4553-8
Electronic_ISBN :
978-1-4673-4551-4
DOI :
10.1109/EPTC.2012.6507066