DocumentCode :
2033253
Title :
Low temperature wafer bonding of CMOS wafers
Author :
Dragoi, Viorel ; Matthias, T. ; Rebhan, B. ; Huysmans, F.
Author_Institution :
EV Group, St. Florian am Inn, Austria
fYear :
2012
fDate :
5-7 Dec. 2012
Firstpage :
197
Lastpage :
201
Abstract :
The continuous need for consumer electronics miniaturization requires not only size shrinking, but also higher degree of integration. The new demands imposed wafer bonding as an attractive technology for wafer-level integration. The resulting increased complexity of the devices brings new challenges to the processing techniques. In manufacturing processes wafer bonding can be used for integration of the electronic components (e.g. Complementary Metal-Oxide- Semiconductor - CMOS - circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. Wafer bonding using CMOS wafers brings additional challenges due to very strict specific requirements, particularly in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.
Keywords :
CMOS integrated circuits; contamination; optical elements; wafer bonding; wafer level packaging; CMOS wafers; consumer electronics miniaturization; contamination; electronic components; low temperature wafer bonding; manufacturing processes wafer bonding; mechanical components; optical components; process temperature; wafer-level integration; wafer-level process step; Annealing; Bonding; CMOS integrated circuits; Metals; Plasma temperature; Surface treatment; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-4553-8
Electronic_ISBN :
978-1-4673-4551-4
Type :
conf
DOI :
10.1109/EPTC.2012.6507077
Filename :
6507077
Link To Document :
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