• DocumentCode
    2033390
  • Title

    VSTA: A prolog-Based Formal Verifier for Systtolic Array Designs

  • Author

    Ling, Nam ; Shih, Timorhy

  • Author_Institution
    Santa Clara University, Santa Clara, CA.
  • Volume
    2
  • fYear
    1993
  • fDate
    16-20 Aug. 1993
  • Firstpage
    73
  • Lastpage
    76
  • Abstract
    Special purpose formal design verifier for a specific class of archirecture has the advantage of being able to exploit the dtributes of that architecture class to produce efficiency in the design verrification process.
  • Keywords
    Concurrent computing; Debugging; Delay; Encoding; Formal verification; Hip; Parallel processing; Process design; Systolic arrays; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing, 1993. ICPP 1993. International Conference on
  • Conference_Location
    Syracuse, NY, USA
  • ISSN
    0190-3918
  • Print_ISBN
    0-8493-8983-6
  • Type

    conf

  • DOI
    10.1109/ICPP.1993.185
  • Filename
    4134187
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2033390