Title :
Acceleration of analog simulation by partial LU decomposition
Author_Institution :
Lucent Technol., Allentown, PA, USA
Abstract :
This paper presents a method for accelerating analog simulation by incrementally updating the admittance matrix, and re-solving only the part of the matrix that depends on the factors that changed. There is substantial speedup for large linear subcircuits of the type generated by RLGC extractors for interconnect analysis, and for large circuits exploiting latency. It makes little if any difference for small nonlinear circuits
Keywords :
analogue integrated circuits; circuit analysis computing; electric admittance; linear network analysis; matrix decomposition; RLGC extractors; admittance matrix; analog simulation acceleration; incremental matrix updating; interconnect analysis; large linear subcircuits; latency; partial LU decomposition; Acceleration; Admittance; Circuit simulation; Costs; Integrated circuit interconnections; Matrices; Matrix decomposition; Nonlinear circuits; Roundoff errors;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.594159
