3D embedded wafer-level packaging technology development for smart card SIP application

Author

Pares, G. ; Bouvier, Cyril ; Saadaoui, Mohamed ; Mazuir, J. ; Noiray, J. ; Martinschitz, K. ; Planchais, A. ; Simon, Gael

Author_Institution

MINATEC, CEA-LETI, Grenoble, France

fYear

2012

fDate

5-7 Dec. 2012

Firstpage

304

Lastpage

310

Abstract

Fan-Out wafer level packaging (eWLP) has been proven to be a valuable solution for producing compact multi-die packages with high performances and is from now on in volume production[1-3]. Known good dies are rebuilt in a molding compound matrix wafer and fan out redistribution layer and bumps are subsequently built on top of the as-formed strata. In this work we present a novel ultra-thin 3D-eWLP technology designed for smart-card products integrating heterogeneous ICs in a three stacked strata architecture.

Keywords

microassembling; smart cards; wafer level packaging; 3D embedded wafer-level packaging technology development; compact multidie packages; fan out redistribution bumps; fan out redistribution layer; fan-out wafer level packaging; heterogeneous IC integration; molding compound matrix wafer; smart card SIP application; smart-card products; stacked strata architecture; ultrathin 3D-eWLP technology; volume production; Conferences; Decision support systems; Electronics packaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th

Conference_Location

Singapore

Print_ISBN

978-1-4673-4553-8

Electronic_ISBN

978-1-4673-4551-4

Type

conf

DOI

10.1109/EPTC.2012.6507097

Filename

6507097