Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

Author

Coudrain, P. ; Colonna, Jean-Philippe ; Aumont, Christophe ; Garnier, G. ; Chausse, Pascal ; Segaud, R. ; Vial, K. ; Jouve, A. ; Mourier, T. ; Magis, T. ; Besson, Pierre ; Gabette, L. ; Brunet-Manquat, C. ; Allouti, N. ; Laviron, C. ; Cheramy, S. ; Saugie

Author_Institution

STMicroelectron., Crolles, France

fYear

2012

fDate

5-7 Dec. 2012

Firstpage

330

Lastpage

335

Abstract

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.

Keywords

CMOS integrated circuits; assembling; ball grid arrays; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; three-dimensional integrated circuits; 3D assembly; 3D circuit; BGA; CMOS node; bottom die realization; electrical tests; face-to-back integration; reliability tests; size 65 nm; wide I/O interconnects; Assembly; Etching; Nails; Reliability; Silicon; Stacking; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th

Conference_Location

Singapore

Print_ISBN

978-1-4673-4553-8

Electronic_ISBN

978-1-4673-4551-4

Type

conf

DOI

10.1109/EPTC.2012.6507102

Filename

6507102