Optimization of sense amplifier energy recovery flip-flop

This paper presents a novel sense amplifier energy recovery flip-flop which realizes better area efficiency and less power consumption compared to conventional sense amplifier energy recovery flip-flop. This is achieved by replacing the storage element of conventional sense amplifier energy recovery flip-flop with 2N-2N2P structure which works on the principle of adiabatic logic. The resulting flip-flop outweighs the conventional flip-flop with 22% reduction in power consumption and 10% reduction in silicon area. Reduced power consumption against various energy recovery flip flops such as DCCER (Differential Conditional Capturing Energy Recovery) flip-flop, SCCER (Single-Ended Conditional Capturing Energy Recovery) flip-flop, SDER (Static Differential Energy Recovery) flip-flop is also proved. The simulations have been carried out at a frequency of 100MHz across a voltage range from 2.2V to 3.3V.