Title :
Optimization of sense amplifier energy recovery flip-flop
Author :
Brindha, B. ; Bhaaskaran, V. S Kanchana ; Vinoth, C. ; Kavinilavu, V. ; Sakthikumaran, Samiappa
Author_Institution :
SSN Coll. of Eng., Rajiv Gandhi Salai, Chennai, India
Abstract :
This paper presents a novel sense amplifier energy recovery flip-flop which realizes better area efficiency and less power consumption compared to conventional sense amplifier energy recovery flip-flop. This is achieved by replacing the storage element of conventional sense amplifier energy recovery flip-flop with 2N-2N2P structure which works on the principle of adiabatic logic. The resulting flip-flop outweighs the conventional flip-flop with 22% reduction in power consumption and 10% reduction in silicon area. Reduced power consumption against various energy recovery flip flops such as DCCER (Differential Conditional Capturing Energy Recovery) flip-flop, SCCER (Single-Ended Conditional Capturing Energy Recovery) flip-flop, SDER (Static Differential Energy Recovery) flip-flop is also proved. The simulations have been carried out at a frequency of 100MHz across a voltage range from 2.2V to 3.3V.
Keywords :
flip-flops; logic design; 2N-2N2P structure; DCCER; SCCER; SDER; adiabatic logic; differential conditional capturing energy recovery; frequency 100 MHz; power consumption; sense amplifier energy recovery flip-flop; silicon area; single-ended conditional capturing energy recovery; static differential energy recovery flip-flop; storage element; voltage 2.2 V to 3.3 V; Clocks; Flip-flops; Latches; Logic gates; Power demand; Strontium; Transistors; Energy Recovery Logic; Flip-Flops; Low power VLSI Circuits;
Conference_Titel :
Electronics Computer Technology (ICECT), 2011 3rd International Conference on
Conference_Location :
Kanyakumari
Print_ISBN :
978-1-4244-8678-6
Electronic_ISBN :
978-1-4244-8679-3
DOI :
10.1109/ICECTECH.2011.5941614
