Packaging challenges for small die

During the last few years, wafer technology has been shrinking aggressively from the 50nm node down to a much smaller technology node. This creates a disparity between die and packaging in which the die is miniaturizing, yet the packaging´s physical footprint remains unchanged. Among the various packaging types, the one that is most impacted is board-on-chip (BOC) packaging, which is the current mainstream packaging for DDR2/DDR3 devices. The construction of the BOC package is a one-layer interposer with a window cut-out along the center; the die´s active circuit faces down with respect to the package footprint. The interconnect between the die and package is wire, via the window cut-out. As the die shrinks, and the package footprint remains unchanged, one of the design bottlenecks is the trace fan-out issue from the bond finger to the innermost column of the ball, as well as the tighter bond finger pitch due to the die-pad pitch reduction. This paper will describe the design features that need be addressed for small-die packages - for example, the drive toward fine line trace, wire bond top pad width, and narrower bond slots. A test vehicle is tooled up as a simulation of possible manufacturing/process issues for the small-die package solution. The design and analysis of the experiment are described in full in this paper.