Analysis of signal integrity(SI) robustness in through-silicon interposer (TSI) interconnects

Author

Weerasekera, Roshan ; Cubillo, Joseph Romen ; Katti, Guruprasad

Author_Institution

Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore

fYear

2012

fDate

5-7 Dec. 2012

Firstpage

397

Lastpage

398

Abstract

This paper describes the electrical characteristics of the fine pitch interconnects in silicon carrier systems. The characteristics of such interconnects are explored and a typical FPGA-memory system is compared viz-a-viz with a traditional PCB system from low data rates to higher data rates. Our case-study shows that even though highly resistive wires are used in silicon carrier the interconnects are SI robust due to the shorter die to die interconnect length and the absence of package parasitics.

Keywords

field programmable gate arrays; integrated circuit interconnections; integrated circuit packaging; integrated logic circuits; three-dimensional integrated circuits; FPGA memory system; die to die interconnect; fine pitch interconnects; package parasitic; signal integrity robustness; silicon carrier system; through-silicon interposer interconnects; Bandwidth; Capacitance; Integrated circuit interconnections; Robustness; Silicon; Timing; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th

Conference_Location

Singapore

Print_ISBN

978-1-4673-4553-8

Electronic_ISBN

978-1-4673-4551-4

Type

conf

DOI

10.1109/EPTC.2012.6507115

Filename

6507115