Deep Trench Resistance and leakage Reduction - Poly1 Doping Process Optimization in High Volume DRAM Manufacturing for 300mm Factory

Author

Kim, Min-Soo ; Cooper, William ; Simonson, Brian ; Ricks, David ; McDaniel, Eric ; Miller, Roderick ; Chapman, Richard ; Taylor, Thomas ; Fuller, Robert

Author_Institution

Infineon Technol., Sandston, VA

fYear

2006

fDate

22-24 May 2006

Firstpage

423

Lastpage

427

Abstract

In this paper, we describe the influence of arsenic doped poly-silicon on signal margin and node leakage current of 110 nm deep trench DRAM products. Methods on optimizing both physical and electrical qualities of poly-silicon are presented and challenges of quick electrical characterization of the new process for rapid yield learning are discussed. Finally, how these methods can be applied to other poly layers and to the next generation devices are briefly discussed

Keywords

DRAM chips; arsenic; integrated circuit manufacture; isolation technology; leakage currents; nanotechnology; production facilities; semiconductor doping; silicon; 110 nm; 300 mm; arsenic doped poly-silicon; deep trench DRAM products; deep trench resistance; deep trench technology; furnace loading effect; high volume DRAM manufacturing; leakage reduction; nanofabrication process; node leakage; poly1 doping process; process optimization; rapid yield learning; signal margin; yield enhancement; CMOS technology; Capacitors; Doping; Furnaces; Leakage current; Manufacturing processes; Optimization methods; Production facilities; Random access memory; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

1-4244-0254-9

Type

conf

DOI

10.1109/ASMC.2006.1638795

Filename

1638795