Reduced comparator low power flash ADC using 35nm CMOS

ADC is one of the basic elements in digital system, as we need to interconnect the digital system to real world that is analog, so these are a primary and important block of any digital system. In this paper, a new design for a low power CMOS flash ADC is proposed. A 4 bit flash ADC with maximum acquisition speed of 2Gs/s, is implemented with 1.2V supply voltage. Hspice simulation result for proposed architecture verifying the analytical result is given. It shows that the proposed ADC consumes about 24mW. The INL/DNL is 0.34/0.4. This is due to reduction in number of comparators as compared to normal flash ADC. By reduced no of comparator.