Title :
Exhaustive testing of Fused Multiply-Add RTL
Author :
Burgess, Neil ; Lutz, David R.
Author_Institution :
ARM, Austin, TX, USA
Abstract :
This paper describes the development and use of a short-wordlength (11-bit) Fused Multiply-Add (“FMA”) design. This “cut-down” design replicates the logic of our IEEE 754-2008 compliant FMA RTL, but the smaller size permits exhaustive testing. We present details of the complete test results and discuss the utility of the truncated FMA.
Keywords :
floating point arithmetic; logic design; logic testing; IEEE 754-2008 compliant FMA RTL; cut-down design; fused multiply-add RTL exhaustive testing; short-wordlength FMA design; word length 11 bit; Computer bugs; Floating-point arithmetic; IEEE standards; Multiplexing; Process control; Testing; Vectors;
Conference_Titel :
Signals, Systems and Computers, 2013 Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4799-2388-5
DOI :
10.1109/ACSSC.2013.6810306
