• DocumentCode
    2035061
  • Title

    Architecture for VLSI implementation of discrete cosine transform processor for video codec

  • Author

    Jain, P.C.

  • Author_Institution
    Central Electron. Eng. Res. Inst., Pilani, India
  • Volume
    1
  • fYear
    1993
  • fDate
    19-21 Oct. 1993
  • Firstpage
    28
  • Abstract
    A VLSI chip having a small number of arithmetic components to implement the Discrete Cosine Transform (DCT) in real time is desirable. In this paper various fast algorithms are taken into considerations to find the minimum necessary arithmetic components.<>
  • Keywords
    VLSI; codecs; digital signal processing chips; discrete cosine transforms; Discrete Cosine Transform; VLSI chip; VLSI implementation; discrete cosine transform processor; fast algorithms; video codec; Arithmetic; Computer simulation; Discrete cosine transforms; Discrete transforms; Hardware; Image coding; Karhunen-Loeve transforms; Transform coding; Very large scale integration; Video codecs;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
  • Conference_Location
    Beijing, China
  • Print_ISBN
    0-7803-1233-3
  • Type

    conf

  • DOI
    10.1109/TENCON.1993.319920
  • Filename
    319920
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2035061