Title :
4-stage pipeline architecture
Author_Institution :
Comput. Sci. Group, BITS, Pilani, India
Abstract :
Pipelined architectures have advantages over conventional processor design. In this paper, using a four-stage pipelining in the architecture of a contemporary processor, the design illustrates a 30% decrease in output of a single task when four tasks are concurrently executed. Throughput of the processor can increase up to 270%. The cost effectivity is enhanced by using a single set of peripherals. Effective comparison of the 4-stage pipelined processor is also presented.<>
Keywords :
parallel architectures; performance evaluation; pipeline processing; 4-stage pipelined processor; architecture; concurrently executed; parallel architecture; performance; pipeline architecture; throughput; Clocks; Computer architecture; Costs; Counting circuits; Parallel processing; Pipeline processing; Process control; Process design; Synchronization; Throughput;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.319922
