Title :
Fault tolerance and pipelining of VLSI combinational logic networks
Author :
Jiang Jianhui ; Hu Mou
Author_Institution :
Dept. of Comput. Eng., Shanghai Inst. of Railway Technol., China
Abstract :
On the basis of alternating logic and complementary logic, a new fault-tolerant design method named as alternate complementary logic is proposed. Some properties of this logic are analyzed and a scheme of the combinational network realizing an arbitrary alternate complementary logic function is proposed. Under the assumption of the stuck-fault model, the network has the capabilities of on-line self-testing and fault-masking, and its time-delay can be reduced by pipelining.<>
Keywords :
VLSI; circuit reliability; combinatorial circuits; logic testing; VLSI combinational logic networks; arbitrary alternate complementary logic function; fault tolerance; fault-masking; pipelining; self-testing; stuck-fault model; time-delay; Built-in self-test; Circuit faults; Design methodology; Fault tolerance; Logic design; Logic functions; Logic testing; Pipeline processing; Redundancy; Very large scale integration;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.319924
