• DocumentCode
    2035352
  • Title

    Validation of stepwise refinement with test cases generated from formal specification

  • Author

    Yamada, Shinya ; Keijiro, Araki ; Kusakabe, Shigeru ; Omori, Yoichi

  • Author_Institution
    Kyushu Univ., Fukuoka, Japan
  • fYear
    2010
  • fDate
    21-24 Nov. 2010
  • Firstpage
    2449
  • Lastpage
    2453
  • Abstract
    In software development, there is a problem that development cost increases by back track when bugs which are included in the phase of requirement definition are found in the after phases. As an effective method to solve the problem, we have a method with a formal specification language for requirement. A formal specification language can describe the functional requirement exactly with mathematical in and verifies the specification with tools. In formal method, we change the specification in a formal specification to executable program with stepwise refinement. At stepwise refinement step, we find bugs by proof of the specification. Herewith, we can get the program of the high level reliability. But, it is expensive to develop with proof. There is a method to verify specification with test cases generated by manpower. But, there are possibilities of including bugs in specification because of generating by manpower. We propose the method to validate stepwise refinement with lightweight method. We generate test cases from formal specification in VDM-SL before refinement, and test the specification after refinement. With this validation method, it is possible to validate of refinement focused state transition model. We implemented test case generator tool whose test case is executed with VDMUnit and VDMTools. We can confirm the availability of the validation of refinement with test case generator tool we implemented.
  • Keywords
    Vienna development method; formal languages; formal specification; formal verification; program debugging; refinement calculus; software reliability; VDM-SL; VDMTool; VDMUnit; formal specification; formal specification language; high level reliability; program debugging; software development; state transition model; stepwise refinement validation; test case generation; FSA; Jermy Dick´s method; formal specification; generator tool; stepwise refinement; test case; validation; verification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2010 - 2010 IEEE Region 10 Conference
  • Conference_Location
    Fukuoka
  • ISSN
    pending
  • Print_ISBN
    978-1-4244-6889-8
  • Type

    conf

  • DOI
    10.1109/TENCON.2010.5685923
  • Filename
    5685923