A cost-effective scheme for at-speed self-test

Author

Xiaowei Li ; Fuqing Yang

Author_Institution

Dept. of Comput. Sci. & Technol., Beijing Univ., China

Volume

1

fYear

1993

fDate

19-21 Oct. 1993

Firstpage

89

Abstract

A serial feedback-based scheme for at-speed self-test is proposed in this paper. By using on-chip feedback lines to link pseudo random pattern generator (PRPG) and multiple input signature analysis register (MISR), aliasing can be reduced, compared to a conventional output register MISR. The analysis of state transition graph (STG) topology revealed that it is possible to design a serial feedback-based built-in self test (BIST) structure yielding STGs of disjunct rings only. Experimental results on ISCAS´85 benchmark circuits are presented.<>

Keywords

built-in self test; feedback; logic testing; ISCAS´85 benchmark circuits; aliasing; at-speed self-test; built-in self test; multiple input signature analysis register; on-chip feedback lines; pseudo random pattern generator; serial feedback-based scheme; state transition graph topology; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Circuit topology; Computer science; Feedback; Shift registers; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on

Conference_Location

Beijing, China

Print_ISBN

0-7803-1233-3

Type

conf

DOI

10.1109/TENCON.1993.319934

Filename

319934