Design-oriented delay model for CMOS inverter

Author

Marranghello, Felipe S. ; Reis, André I. ; Ribas, Renato P.

Author_Institution

Inst. of Inf., Fed. Univ. of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil

fYear

2012

fDate

Aug. 30 2012-Sept. 2 2012

Firstpage

1

Lastpage

6

Abstract

This paper presents a new design oriented model for estimating the delay of a CMOS inverter. The model considers the impact of input transition time, input-to-output coupling capacitance, and physical effects such as drain-induced barrier lowering (DIBL) and velocity saturation. Thus, it is quite suitable for nanometer technologies. Moreover, no fitting parameters are required. Results are in very good agreement with HSPICE simulations based on BSIM4 transistor model over a wide range of input slopes and output loads, considering different inverter configurations. An average error of 3% in correlation to HSPICE has been attained.

Keywords

CMOS integrated circuits; capacitance; invertors; BSIM4 transistor model; CMOS inverter; HSPICE simulation; design oriented delay model; drain induced barrier lowering; input-to-output coupling capacitance; inverter configuration; nanometer technology; velocity saturation; Iron; Manganese; Zinc; formatting; insert; style; styling;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on

Conference_Location

Brasilia

Print_ISBN

978-1-4673-2606-3

Type

conf

DOI

10.1109/SBCCI.2012.6344424

Filename

6344424