Evaluating the relative effect of process variations and switching patterns on bus performance towards nano-scale interconnects

In this paper the authors examined and compared the relative contribution between a switching pattern and process parameter variation on bus performance. The authors concentrated on interconnect parameter variation in global bus interconnects. The variation of the parameter values between individual interconnects occurs when process technologies head towards nano-scale. In addition to this "passive" process-dependent parameter variation active variation in interconnect performance due to switching data patterns in adjacent wires of a bus structure were examined. A noise voltage in a quiet wire and the propagation delay of a signal are performance metrics in the comparisons. The effect of signal rise time is also considered. The comparisons were made using International Technology Roadmaps for Semiconductors (ITRS) from a 180-nm half-pitch node to a 22-nm node.