On a hardware architecture for the evolution of cellular automata functionality

The authors described the architecture of a cellular automaton used as a hardware accelerator in the evaluation loop or a genetic algorithm (GA). Cellular automata are basic computational structures of interacting units which are capable of exposing self-organization and emergent behavior. To investigate this behavior subject to different cell interconnect patterns, an automated inspection flow is needed, including a very fast evaluation of single specimen. The solution consists of a distributed software environment for a parallel simulation, where server processes can encapsulate a hardware accelerator instead of a software simulation. Here the focus is on the hardware implementation: a flexible FPGA-based accelerator for cellular automata evaluation which is accessed transparently by a GA Java client. First results show moderate area requirements allowing an FPGA implementation and a clock frequency of up to about 130 MHz raw transition performance.