Parallel 4×4 transform architecture based on bit extended arithmetic for H.264/AVC

H.264/AVC, the latest standard for the coding of video signal, utilizes a 4×4 integer transform to concentrate energy of residual data in a few coefficients. In this paper, a new parallel 4×4 transform architecture based on bit extended arithmetic is proposed for H.264/AVC. Compared with the existing parallel architecture, the proposed architecture eliminates redundant logic through bit extended arithmetic. Simulation results show that the hardware complexity is decreased by 25% and the data processing rate is increased by 16%.