A chip to embedded system test process using IEEE 1149.1 boundary scan

Author

Kadaras, Joseph E.

Author_Institution

Mercury Comput. Syst. Inc., Chelmsford, MA, USA

fYear

1994

fDate

10-12 May 1994

Firstpage

728

Lastpage

732

Abstract

Considerable progress has been made over the past few years in design for test (DFT) techniques, and its propagation into the mind-set of design engineers. No longer are designers having test after-thoughts; test has become a critical part in product prototype and introduction cycles. This mind-set becomes more prevalent with the advent of IEEE 1149.1 boundary scan, and its design implementation requirements for success. This paper discusses a boundary scan test strategy and implementation for a new extremely dense, ruggedized embedded processor which delivers a peak compute performance of 10GFlops/cubic foot. The system´s architects and design engineers recognized the need for DFT, and implemented IEEE 1149.1 boundary scan and a TI 8990 test bus controller to insure not only their success during proto debug, but the overall product´s success in manufacturing and after deployment

Keywords

IEEE standards; boundary scan testing; computer testing; design for testability; integrated circuit testing; IEEE 1149.1 boundary scan; TI 8990 test bus controller; design for test techniques; design implementation requirements; embedded system test process; peak compute performance; ruggedized embedded processor; Application specific integrated circuits; Computer architecture; Design engineering; Design for testability; Embedded computing; Embedded system; Engineering management; Foot; Prototypes; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electro/94 International. Conference Proceedings. Combined Volumes.

Conference_Location

Boston, MA

Print_ISBN

0-7803-2630-X

Type

conf

DOI

10.1109/ELECTR.1994.472652

Filename

472652