An embedded JTAG, system test architecture

Author

Andrews, John

Author_Institution

Nat. Semicond. Corp., South Portland, ME, USA

fYear

1994

fDate

10-12 May 1994

Firstpage

691

Lastpage

695

Abstract

IEEE 1149.1, The Standard Test Access Port and Boundary-Scan Architecture (JTAG) was written to provide standardized test access to surface mounted integrated circuits (ICs) whose high density packaging restricted physical test access. Although the four-wire (optionally five-wire) test port defined within the standard is commonly applied to test printed circuit boards (PCBs) in a factory, there is not yet a standard method for testing modules once they are installed in a system. This paper describes an architecture for extending the application of JTAG to system-level testing. It assumes reader familiarity with IEEE 1149.1

Keywords

IEEE standards; printed circuit testing; surface mount technology; Boundary-Scan Architecture; IEEE 1149.1; Standard Test Access Port; embedded JTAG; high density packaging; printed circuit boards testing; surface mounted integrated circuits; system test architecture; system-level testing; Access protocols; Backplanes; Circuit testing; Embedded system; Integrated circuit packaging; Integrated circuit testing; Printed circuits; Production facilities; Semiconductor device packaging; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electro/94 International. Conference Proceedings. Combined Volumes.

Conference_Location

Boston, MA

Print_ISBN

0-7803-2630-X

Type

conf

DOI

10.1109/ELECTR.1994.472654

Filename

472654