DocumentCode
2035977
Title
Development of a single step via tapering etch process using deep reactive ion etching with low sidewall roughness for through-silicon via applications
Author
Praveen, S.K. ; Zain, M.F.M. ; Zhang Qing Xin ; Johnson, D.
Author_Institution
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear
2012
fDate
5-7 Dec. 2012
Firstpage
732
Lastpage
735
Abstract
This paper discusses the importance of having a tapered via in TSV integration processes and the various ways currently used to achieve it. In addition, a novel way of creating this tapered via with single step Deep Reactive Ion Etching (DRIE) process to achieve it is also presented.
Keywords
sputter etching; three-dimensional integrated circuits; TSV integration processes; deep reactive ion etching; low sidewall roughness; single step DRIE process; single step deep reactive ion etching process; single step development; tapering etch process; through-silicon via applications; Etching; Passivation; Plasmas; Silicon; Standards; Sulfur hexafluoride; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th
Conference_Location
Singapore
Print_ISBN
978-1-4673-4553-8
Electronic_ISBN
978-1-4673-4551-4
Type
conf
DOI
10.1109/EPTC.2012.6507179
Filename
6507179
Link To Document