Hardware and software co-design for the AAC audio decoder

This paper presents a HW/SW Co-design of an AAC-LC audio decoder implemented on an FPGA. The complexity of each decoding step is analyzed and the decoding modules are classified by their computational requirements. The result is a balanced design with software modules running on a processor used to implement the various types of AAC input formats (MP4 Standard files and LATM/LOAS Stream) as well as the bitstream parser. Hardware modules are used for the calculation intensive parts of the algorithm (Huffman Decoding, Spectral Tools, Filterbank). The integrated design is implemented on an Altera Cyclone II FPGA with NIOS II/s as a processor and was able to decode 5.1 (6 channels) audio wavefiles running at 50MHz while other FPGA designs seen on literature decode only 2 channels with half the frequency.