Copper filling of TSVs for interposer applications

Author

Jurgensen, Nils ; Huynh, Q.H. ; Engelmann, Georges ; Ngo, Hau ; Ehrmann, O. ; Lang, Klaus-Dieter ; Uhlig, A. ; Dretschkow, T. ; Rohde, David ; Worm, O. ; Jager, Claus

Author_Institution

Fraunhofer Inst. for Reliability & Microintegration, Berlin, Germany

fYear

2012

fDate

5-7 Dec. 2012

Firstpage

759

Lastpage

763

Abstract

For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as their quantity on the wafer have a severe influence on the electrochemical process parameters, in particular on the current process time profile. So the electrochemical deposition (ECD) current was investigated in dependence of the filling progress, the height-to-depth aspect ratio, and the quantity of high aspect ratio vias on the wafer. The same applies to the number of plating steps at constant current, their length, and the total process time. Valuable insights for the design of via filing recipes could be deduce thereof.

Keywords

copper; electrodeposition; integrated circuit interconnections; integrated circuit packaging; three-dimensional integrated circuits; TSV; aspect ratio; copper filling; electrochemical deposition; electrochemical filling; electrochemical process parameters; process time profile; through-silicon-via; Anodes; Copper; Current density; Filling; Geometry; Surface treatment; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th

Conference_Location

Singapore

Print_ISBN

978-1-4673-4553-8

Electronic_ISBN

978-1-4673-4551-4

Type

conf

DOI

10.1109/EPTC.2012.6507186

Filename

6507186