MFBIST: a BIST method for random pattern resistant circuits

This paper presents a test per clock BIST technique that uses multiple idler register segments with selective bit-fixing driven by multiple biased pseudorandom pattern generators to provide 100% fault coverage of detectable single stuck-at faults. The technique is particularly effective for random pattern resistant circuits. A BIST architecture that supports this technique, and a design tool (MFBIST) that implements the technique are presented. The amount of hardware overhead is controlled by user-specified parameters and can meet varying design specifications. Results and comparisons with prior techniques are presented for combinational benchmarks and combinational versions of sequential benchmark circuits. To better evaluate hardware overhead, automatic CMOS layouts were performed for the benchmark circuits. The results show that the additional area overhead, relative to that required by pseudorandom test per clock designs, is small