DocumentCode :
2036395
Title :
An automatic testing technique for PLDs
Author :
ElSayed, Ahmed ; Elbably, Mohmed ; Elbolok, Hatern
Author_Institution :
Fac. of Eng., Helwan Univ., Cairo, Egypt
fYear :
2002
fDate :
2002
Firstpage :
413
Lastpage :
420
Abstract :
The programmable logic devices (PLDs) are widely used in the hardware implementation of many designed circuits. Identifying the faulty row, which contains many configurable logic blocks (CLBs) was the aim of many researchers. A. new technique is proposed in this research. The main aim of the proposed technique concentrates on identifying the location of the faculty CLB in FPGA (field programmable gate array) chips.
Keywords :
automatic testing; fault location; field programmable gate arrays; integrated circuit testing; programmable logic devices; FPGA chips; PLD; XC4000E/XC4000X FPGA series; automatic testing; configurable logic blocks; fault location; field programmable gate array; hardware implementation; programmable logic devices; Automatic testing; Circuit faults; Fault diagnosis; Field programmable gate arrays; Flip-flops; Logic functions; Multiplexing; Multiprocessor interconnection networks; Packaging; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radio Science Conference, 2002. (NRSC 2002). Proceedings of the Nineteenth National
Print_ISBN :
977-5031-72-9
Type :
conf
DOI :
10.1109/NRSC.2002.1022649
Filename :
1022649
Link To Document :
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