Automatic synthesis of VHDL benchmarks to support simulation performance evaluation

This paper discusses the issues and potential solutions to the problem of creating benchmarks for evaluating the performance of large parallel VHDL simulators. Automatically creating VHDL programs with known functional and performance characteristics such as maximum potential parallelism, expected computation-to-communication time ratios, and feature sizes is suggested as a low-cost accurate substitute for VHDL benchmarks created by manual methods. An approach to synthetically creating VHDL benchmarks is described. The use of synthetic benchmarks for imitating the desired characteristics of real VHDL code is also addressed