Specification of interface behavior for the automatic generation of bus-interface models

This paper describes SpecIT, a tool that captures a high-level specification of bus-interface behavior and automatically generates VHDL and Verilog models. SpecIT users need not be familiar with either VHDL or Verilog, instead interface behavior is specified graphically using familiar hardware constructs such as state diagrams, timing diagrams, and truth tables. SpecIT substantially reduces the time required to create bus-interface models