DocumentCode
2036574
Title
Improving test quality through resource reallocation
Author
Adir, Allon ; Marcus, Eitan ; Rimon, Michal ; Voskoboynik, Amir
Author_Institution
IBM Res. Lab, Haifa, Israel
fYear
2001
fDate
2001
Firstpage
64
Lastpage
69
Abstract
Test program generation typically involves the resolution of constraints to make the tests legal and interesting for verification. This is often achieved through the values of resources used by the instructions in the test. The difficulty is that the number of available resources is limited, and there may be fewer available resources than needed values (especially in long tests). One way to get a large number of values from a limited number of resources, is to insert value-assigning instructions into the test before the instruction that is to use the resource´s value. We refer to this as resource reloading. This paper presents a reloading technique that minimizes the interference caused. by the reloading instructions and avoids fixed code patterns by distancing the reloading instruction from the instruction that uses the resource value. The basic technique is presented along with several useful extensions and is compared with other reloading approaches
Keywords
high level synthesis; logic testing; microprocessor chips; micro-architectural specifications; processor design; processor functional verification; resource reallocation; resource reloading; test program generation; value-assigning instructions; Automatic testing; Interference; Law; Legal factors; Microarchitecture; Process design; Random number generation; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International
Conference_Location
Monterey, CA
Print_ISBN
0-7695-1411-1
Type
conf
DOI
10.1109/HLDVT.2001.972809
Filename
972809
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