• DocumentCode
    2036690
  • Title

    Combining complex event models and timing constraints

  • Author

    Jersak, Marek ; Richter, Kai ; Ernst, Rolf

  • Author_Institution
    Inst. of Comput. & Commun. Network Eng. (IDA), Technische Univ. Braunschweig, Germany
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    89
  • Lastpage
    94
  • Abstract
    Sophisticated models of event streams including jitter and bursts as well as the possibility to specify a variety of system-level timing constraints are prerequisites for modem analysis and synthesis techniques in the area of embedded real-time systems. Currently, there is no commonly used specification that models events and timing constraints in a sufficiently general way. In this paper, we first identify a duality between event models and timing constraints and as a result present a specification that can be used for both. Our specification covers most current analysis and synthesis techniques and is easily extensible. We then show how the duality between event models and timing constraints can be applied at different points in a design flow. A real-time video transmission is used as an example
  • Keywords
    embedded systems; formal specification; high level synthesis; timing; timing jitter; bursts; embedded real-time systems; event models; event streams; jitter; real-time video transmission; specification; system-level timing constraints; timing constraints; Clocks; Communication networks; Computer networks; Delay; Embedded computing; Embedded system; Network synthesis; Real time systems; System testing; Timing jitter;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2001. Proceedings. Sixth IEEE International
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    0-7695-1411-1
  • Type

    conf

  • DOI
    10.1109/HLDVT.2001.972813
  • Filename
    972813